Quantifying Locality in the Memory Access Patterns of HPCApplications
Several benchmarks for measuring memory performance of HPC systems along dimensions of spatial and temporal memory locality have recently been proposed. However, little is understood about the relationships of these benchmarks to real applications and to each other. In this paper, we propose a methodology for producing architecture-neutral characterizations of the spatial and temporal locality exhibited by the memory access patterns of applications. We demonstrate that the results track intuitive notions of spatial and temporal locality on several synthetic and application benchmarks. We employ the methodology to analyze the memory performance components of the HPC Challenge Benchmarks, the Apex-MAP benchmark, and their relationships to each other and other benchmarks and applications. We show that this analysis can be used to both increase understanding of the benchmarks and enhance their usefulness by mapping them, along with applications, to a 2-D space along axes of spatial and temporal locality.
- Research Organization:
- Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States)
- Sponsoring Organization:
- USDOE Director. Office of Science. Office of AdvancedScientific Computing Research; National Science Foundation CNS-0406312,Pittsburgh Superconducting Center NSF NRAC Award
- DOE Contract Number:
- DE-AC02-05CH11231
- OSTI ID:
- 876214
- Report Number(s):
- LBNL-58441; R&D Project: K11114; BnR: KJ0101030; TRN: US200620%%684
- Resource Relation:
- Conference: SC 2005, Seattle, WA, Nov 12-18,2005
- Country of Publication:
- United States
- Language:
- English
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